1. Field of the Invention
The present invention relates to integrated circuits employing metal oxide semiconductor field effect transistor (MOSFET) circuitry, in and particular, to ICs employing MOSFET circuitry having internal compensation for variations among the processing (P) of, power supply voltage (V) for, and operating temperature (T) of the IC (otherwise known as PVT).
2. Description of the Related Art
As is well-known, IC densities have been increasing as generations of IC fabrication processes have become more sophisticated. Increases in density are achieved primarily by reducing the sizes, e.g., channel lengths and widths, of the MOSFETs. With such decreases in dimensions, power supply voltages have also decreased. One benefit of this is generally lower power dissipation. However, power supply voltages have become so low that inherent operating characteristics of the transistors have become limiting factors in performance of the circuits. For example, one such limiting factor in analog circuits employing MOSFETs is the drain-to-source voltage VDS of the MOSFET devices when operated in the generally desired state of saturation. This output saturation voltage VDSAT, as is well-known, is the minimum voltage required between the drain and source terminals for the transistor to remain operating in its saturation region.
Conventional techniques for attempting to maintain some consistency in operating parameters include biasing selected portions of the circuitry to either maintain a constant transconductance (gm) or a constant drain current (id). However, as illustrated by equations 1-3below (where K′ equals the product of the majority carrier mobility u and the gate capacitance per unit area Cox), maintaining a fixed transconductance or fixed drain current results in a variable output saturation voltage VDSAT.             Equation      ⁢                           ⁢      1      ⁢              :              ⁢                       id    =                                        K            ′                    ⁢          W                          2          ⁢          L                    ⁢                        (                      Vgs            -            Vt                    )                2                        Equation      ⁢                           ⁢      2      ⁢              :              ⁢                       gm    =                            δ          ⁢                                           ⁢          id                          δ          ⁢                                           ⁢          Vgs                    =                                                                  K                ′                            ⁢              W                        L                    ⁢                      (                          Vgs              -              Vt                        )                          =                              2            ⁢            id                    VDSAT                                Equation      ⁢                           ⁢      3      ⁢              :              ⁢                             gm      id        =          2      VDSAT      
In many instances, variations in PVT can cause the output saturation voltage VDSAT to change by a factor of 2-3 when either the transconductance or drain current is fixed. Accordingly, these techniques are inadequate for low voltage circuits where the output saturation voltage VDSAT directly determines the output voltage range, and, therefore, the dynamic output signal range, that an amplifier may have. A typical example would be a simple N-type MOSFET output stage with a P-type MOSFET load. Such an amplifier will have an output dynamic signal range approximately equal to the difference between the power supply voltage and two output saturation voltages, i.e., VDD−2*VDSAT. Assuming that the MOSFETs are designed with a nominal output saturation voltage VDSAT of 150 millivolts and the power supply voltage VDD is 1.0 volt, such amplifier will have a nominal output dynamic signal range of 0.7 volt (=1.0−*0.15). However, if the output saturation voltage VDSAT varies by a factor of three, a dynamic output signal voltage range will decrease to only 0.1 volt (=1.0−3*2*0.15).